// +build f030x8

// Peripheral: DMA_Channel_Periph  DMA Controller.
// Instances:
//  DMA1_Channel1  mmap.DMA1_Channel1_BASE
//  DMA1_Channel2  mmap.DMA1_Channel2_BASE
//  DMA1_Channel3  mmap.DMA1_Channel3_BASE
//  DMA1_Channel4  mmap.DMA1_Channel4_BASE
//  DMA1_Channel5  mmap.DMA1_Channel5_BASE
// Registers:
//  0x00 32  CCR   DMA channel x configuration register.
//  0x04 32  CNDTR DMA channel x number of data register.
//  0x08 32  CPAR  DMA channel x peripheral address register.
//  0x0C 32  CMAR  DMA channel x memory address register.
// Import:
//  stm32/o/f030x8/mmap
package dma

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	EN      CCR = 0x01 << 0  //+ Channel enable.
	TCIE    CCR = 0x01 << 1  //+ Transfer complete interrupt enable.
	HTIE    CCR = 0x01 << 2  //+ Half Transfer interrupt enable.
	TEIE    CCR = 0x01 << 3  //+ Transfer error interrupt enable.
	DIR     CCR = 0x01 << 4  //+ Data transfer direction.
	CIRC    CCR = 0x01 << 5  //+ Circular mode.
	PINC    CCR = 0x01 << 6  //+ Peripheral increment mode.
	MINC    CCR = 0x01 << 7  //+ Memory increment mode.
	PSIZE   CCR = 0x03 << 8  //+ PSIZE[1:0] bits (Peripheral size).
	MSIZE   CCR = 0x03 << 10 //+ MSIZE[1:0] bits (Memory size).
	PL      CCR = 0x03 << 12 //+ PL[1:0] bits(Channel Priority level).
	MEM2MEM CCR = 0x01 << 14 //+ Memory to memory mode.
)

const (
	ENn      = 0
	TCIEn    = 1
	HTIEn    = 2
	TEIEn    = 3
	DIRn     = 4
	CIRCn    = 5
	PINCn    = 6
	MINCn    = 7
	PSIZEn   = 8
	MSIZEn   = 10
	PLn      = 12
	MEM2MEMn = 14
)

const (
	NDT CNDTR = 0xFFFF << 0 //+ Number of data to Transfer.
)

const (
	NDTn = 0
)

const (
	PA CPAR = 0xFFFFFFFF << 0 //+ Peripheral Address.
)

const (
	PAn = 0
)

const (
	MA CMAR = 0xFFFFFFFF << 0 //+ Memory Address.
)

const (
	MAn = 0
)
